Biography Computer Architecture And Maintenance Book


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This is a user friendly book on Computer Architecture and Maintenance. It treats the subject content from a practical perspective. No knowledge of computer. Buy book Computer Architecture and Maintenance computer architecture and maintenance engineering computer second year by Shrikant S Velankar, Y C. Contents. 1. Motherboard And Its Components. Introduction. Chipset Basics. Architecture of Intel Chipsets. Buses on Motherboard (Expansion OR.

Computer Architecture And Maintenance Book

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Advanced Java Books and PPTs Computer Architecture and Maintenance ( ) The subject helps the students to do the maintenance of the Computer, . Find Computers Computer Architecture Repair Maintenance books online. Get the best Computers Computer Architecture Repair Maintenance books at our. Book Details. For MSBTE, as per semester syllabus E-Scheme ecogenenergy.infoic Year Polytechnic Fourth Semester for Diploma in computer Engineering .

In essence, the processor is the computing part of the computer. A processor is an electronic device capable of manipulating data information in a way specified by a sequence of instructions. The instructions are also known as opcodes or machine code. This sequence of instructions may be altered to suit the application, and, hence, computers are programmable.

A sequence of instructions is what constitutes a program. Instructions in a computer are numbers, just like data. Different numbers, when read and executed by a processor, cause different things to happen. A good analogy is the mechanism of a music box. A music box has a rotating drum with little bumps, and a row of prongs.

S.Chand's Computer Architecture and Maintenance 12113-Msbte, 1/e

As the drum rotates, different prongs in turn are activated by the bumps, and music is produced. In a similar way, the bit patterns of instructions feed into the execution unit of the processor. Different bit patterns activate or deactivate different parts of the processing core. Thus, the bit pattern of a given instruction may activate an addition operation, while another bit pattern may cause a byte to be stored to memory.

A sequence of instructions is a machine-code program. Each type of processor has a different instruction set, meaning that the functionality of the instructions and the bit patterns that activate them varies. Basic System Architecture The processor alone is incapable of successfully performing any tasks. The basic computer system is shown in Figure Basic computer system A microprocessor is a processor implemented usually on a single, integrated circuit. With the exception of those found in some large supercomputers, nearly all modern processors are microprocessors , and the two terms are often used interchangeably.

The range of available microcontrollers is very broad. In this book, we will look at both microprocessors and microcontrollers. Microcontrollers are very similar to System-on-Chip SoC processors, intended for use in conventional computers such as PCs and workstations. Microcontrollers usually have all their memory on-chip and may provide only limited support for external memory devices.

The memory of the computer system contains both the instructions that the processor will execute and the data it will manipulate.

The memory of a computer system is never empty. It always contains something, whether it be instructions, meaningful data, or just the random garbage that appeared in the memory when the system powered up. Instructions are read fetched from memory, while data is both read from and written to memory, as shown in Figure Data flow This form of computer architecture is known as a Von Neumann machine, named after John Von Neumann, one of the originators of the concept.

With very few exceptions, nearly all modern computers follow this form. Von Neumann computers are what can be termed control-flow computers. The steps taken by the computer are governed by the sequential control of a program. In other words, the computer follows a step-by-step program that governs its operation. Tip There are some interesting non-Von Neumann architectures, such as the massively parallel Connection Machine and the nascent efforts at building biological and quantum computers, or neural networks.

A classical Von Neumann machine has several distinguishing characteristics: There is no real difference between data and instructions. A processor can be directed to begin execution at a given point in memory, and it has no way of knowing whether the sequence of numbers beginning at that point is data or instructions.

The processor has no way of telling what is data or what is an instruction. If a number is to be executed by the processor, it is an instruction; if it is to be manipulated, it is data.

Because of this lack of distinction, the processor is capable of changing its instructions treating them as data under program control. And because the processor has no way of distinguishing between data and instruction, it will blindly execute anything that it is given, whether it is a meaningful sequence of instructions or not.

Data has no inherent meaning. There is nothing to distinguish between a number that represents a dot of color in an image and a number that represents a character in a text document. Meaning comes from how these numbers are treated under the execution of a program. Data and instructions share the same memory.

This means that sequences of instructions in a program may be treated as data by another program. A compiler creates a program binary by generating a sequence of numbers instructions in memory. To the compiler, the compiled program is just data, and it is treated as such. It is a program only when the processor begins execution. Similarly, an operating system loading an application program from disk does so by treating the sequence of instructions of that program as data.

The program is loaded to memory just as an image or text file would be, and this is possible due to the shared memory space. Memory is a linear one-dimensional array of storage locations. Each location in the memory space has a unique, sequential address. The address of a memory location is used to specify and select that location.

The address space is the array of all addressable memory locations. Hence, the processor is said to have a 64K address space. Most microprocessors available are standard Von Neumann machines.

The main deviation from this is the Harvard architecture , in which instructions and data have different memory spaces Figure with separate address, data, and control buses for each memory space. This has a number of advantages in that instruction and data fetches can occur concurrently, and the size of an instruction is not set by the size of the standard data unit word.

Harvard architecture Buses A bus is a physical group of signal lines that have a related function. Buses allow for the transfer of electrical signals between different parts of the computer system and thereby transfer information from one device to another. For example, the data bus is the group of signal lines that carry data between the processor and the various subsystems that comprise the computer.

For example, an 8-bit-wide bus transfers 8 bits of data in parallel. The majority of microprocessors available today with some exceptions use the three-bus system architecture Figure The three buses are the address bus , the data bus, and the control bus.

Three-bus system The data bus is bidirectional, the direction of transfer being determined by the processor. The address bus carries the address, which points to the location in memory that the processor is attempting to access.

It is the job of external circuitry to determine in which external device a given memory location exists and to activate that device. This is known as address decoding. The control bus carries information from the processor about the state of the current access, such as whether it is a write or a read operation. The control bus can also carry information back to the processor regarding the current access, such as an address error.

Different processors have different control lines, but there are some control lines that are common among many processors. The control bus may consist of output signals such as read, write, valid address, etc. A processor usually has several input control lines too, such as reset, one or more interrupt lines, and a clock input.

It was a massive machine, filling a very big room with the type of solid hardware that you can really kick. It was quite an experience looking over the old machine. I remember at one stage walking through the disk controller it was the size of small room and looking up at a mass of wires strung overhead.

I asked what they were for. Processor operation There are six basic types of access that a processor can perform with external chips. The internal data storage of the processor is known as its registers. The instructions that are read and executed by the processor control the data flow between the registers and the ALU. A symbolic representation of an ALU is shown in Figure These values, called operands , are typically obtained from two registers, or from one register and a memory location.

The result of the operation is then placed back into a given destination register or memory location. The status outputs indicate any special attributes about the operation, such as whether the result was zero, negative, or if an overflow or carry occurred.

Some processors have separate units for multiplication and division, and for bit shifting, providing faster operation and increased throughput. Each architecture has its own unique ALU features, and this can vary greatly from one processor to another. However, all are just variations on a theme, and all share the common characteristics just described. Interrupts Interrupts also known as traps or exceptions in some processors are a technique of diverting the processor from the execution of the current program so that it may deal with some event that has occurred.

An interrupt is generated in your computer every time you type a key or move the mouse. You can think of it as a hardware-generated function call. Instead, the processor may continue with other tasks. Interrupts can be of varying priorities in some processors, thereby assigning differing importance to the events that can interrupt the processor.

If the processor is servicing a low-priority interrupt, it will pause it in order to service a higher-priority interrupt. However, if the processor is servicing an interrupt and a second, lower-priority interrupt occurs, the processor will ignore that interrupt until it has finished the higher-priority service.

When an interrupt occurs, the usual procedure is for the processor to save its state by pushing its registers and program counter onto the stack. The processor then loads an interrupt vector into the program counter. The interrupt vector is the address at which an interrupt service routine ISR lies. Thus, loading the vector into the program counter causes the processor to begin execution of the ISR, performing whatever service the interrupting device required. This causes the processor to reload its saved state registers and program counter from the stack and resume its original program.

Interrupts are largely transparent to the original program. Processors with shadow registers use these to save their current state, rather than pushing their register bank onto the stack. This saves considerable memory accesses and therefore time when processing an interrupt. If it does not, important state information will be lost.

Upon returning from an ISR, the contents of the shadow registers are swapped back into the main register array.

For some time-critical applications, polling can reduce the time it takes for the processor to respond to a change of state in a peripheral. A better way is for the device to generate an interrupt to the processor when it is ready for a transfer to take place. Small, simple processors may only have one or two interrupt inputs, so several external devices may have to share the interrupt lines of the processor.

When an interrupt occurs, the processor must check each device to determine which one generated the interrupt. This can also be considered a form of polling. The advantage of interrupt polling over ordinary polling is that the polling occurs only when there is a need to service a device. Polling interrupts is suitable only in systems that have a small number of devices; otherwise, the processor will spend too long trying to determine the source of the interrupt. Vectored interrupts reduce considerably the time it takes the processor to determine the source of the interrupt.

If an interrupt request can be generated from more than one source, it is therefore necessary to assign priorities levels to the different interrupts. This can be done in either hardware or software , depending on the particular application.

In this scheme, the processor has numerous interrupt lines, with each interrupt corresponding to a given interrupt vector. Vectored interrupts can be taken one step further. Some processors and devices support the device by actually placing the appropriate vector onto the data bus when they generate an interrupt. This means the system can be even more versatile, so that instead of being limited to one interrupt per peripheral, each device can supply an interrupt vector specific to the event that is causing the interrupt.

However, the processor must support this function, and most do not. Some processors have a feature known as a fast hardware interrupt. With this interrupt, only the program counter is saved. It assumes that the ISR will protect the contents of the registers by manually saving their state as required.

A special and separate interrupt line is used to generate fast interrupts. Software interrupts A software interrupt is generated by an instruction. It is the lowest-priority interrupt and is generally used by programs to request a service to be performed by the system software operating system or firmware.

So why are software interrupts used? For that matter, why use an operating system to perform tasks for us at all? It gets back to compatibility. Jumping to a subroutine calling a function is jumping to a specific address in memory. A future version of the system software may not locate the subroutines at the same addresses as earlier versions.

By using a software interrupt, our program does not need to know where the routines lie. It relies on the entry in the vector table to direct it to the correct location. CISC processors have a single processing unit, external memory, and a relatively small register set and many hundreds of different instructions.

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In many ways, they are just smaller versions of the processing units of mainframe computers from the s. The tendency in processor design throughout the late 70s and early 80s was toward bigger and more complicated instruction sets. The diversity of instructions in a CISC processor can run to well over 1, opcodes in some processors, such as the Motorola This had the advantage of making the job of the assembly-language programmer easier, since you had to write fewer lines of code to get the job done.

As memory was slow and expensive, it also made sense to make each instruction do more. This reduced the number of instructions needed to perform a given function, and thereby reduced memory space and the number of memory accesses required to fetch instructions. As memory got cheaper and faster, and compilers became more efficient, the relative advantages of the CISC approach began to diminish.

One main disadvantage of CISC is that the processors themselves get increasingly complicated as a consequence of supporting such a large and diverse instruction set. The control and instruction decode units are complex and slow, the silicon is large and hard to produce, and they consume a lot of power and therefore generate a lot of heat.

As processors became more advanced, the overheads that CISC imposed on the silicon became oppressive. A given processor feature when considered alone may increase processor performance but may actually decrease the performance of the total system, if it increases the total complexity of the device. It was found that by streamlining the instruction set to the most commonly used instructions, the processors become simpler and faster. Fewer cycles are required to decode and execute each instruction, and the cycles are shorter.

The drawback is that more simpler instructions are required to perform a task, but this is more than made up for in the performance boost to the processor. The realization of this led to a rethink of processor design. The result was the RISC architecture, which has led to the development of very high-performance processors.

The basic philosophy behind RISC is to move the complexity from the silicon to the language compiler. The hardware is kept as simple and fast as possible. A given complex instruction can be performed by a sequence of much simpler instructions. For example, many processors have an xor exclusive OR instruction for bit manipulation, and they also have a clear instruction to set a given register to zero. However, a register can also be set to zero by xor-ing it with itself.

Thus, the separate clear instruction is no longer required. It can be replaced with the already present xor. Further, many processors are able to clear a memory location directly by writing a zero to it. That same function can be implemented by clearing a register and then storing that register to the memory location.

The instruction to load a register with a literal number can be replaced with the instruction for clearing a register, followed by an add instruction with the literal number as its operand. Thus, six instructions xor, clear reg , clear memory , load literal , store, and add can be replaced with just three xor, store, and add.

So the following CISC assembly pseudocode: clear 0x ; clear memory location 0x load r1, 5 ; load register 1 with the value 5 becomes the following RISC pseudocode: xor r1,r1 ; clear register 1 store r1,0x ; clear memory location 0x add r1, 5 ; load register 1 with the value 5 The resulting code size is bigger, but the reduced complexity of the instruction decode unit can result in faster overall operation.

Dozens of such code optimizations exist to give RISC its simplicity. RISC processors have a number of distinguishing characteristics. They have large register sets in some architectures numbering over 1, , thereby reducing the number of times the processor must access main memory.

Often-used variables can be left inside the processor, reducing the number of accesses to slow external memory. Compilers of high-level languages such as C take advantage of this to optimize processor performance. By having smaller and simpler instruction decode units, RISC processors have fast instruction execution, and this also reduces the size and power consumption of the processing unit.

Generally, RISC instructions will take only one or two cycles to execute this depends greatly on the particular processor. This is in contrast to instructions for a CISC processor, whose instructions may take many tens of cycles to execute. For example, one instruction integer multiplication on an CISC processor takes 42 cycles to complete. The same instruction on a RISC processor may take just one cycle.

Instructions on a RISC processor have a simple format. All instructions are generally the same length which makes instruction decode units simpler. This means that the only instructions that actually reference memory are load and store.

In contrast, many most instructions on a CISC processor may access or manipulate memory. On a RISC processor, all other instructions aside from load and store work on the registers only. This facilitates the ability of RISC processors to complete most of their instructions in a single cycle.

RISC processors also often have pipelined instruction execution. This means that while one instruction is being executed, the next instruction in the sequence is being decoded, while the third one is being fetched. At any given moment, several instructions will be in the pipeline and in the process of being executed.

Again, this provides improved processor performance. Thus, even though not all instructions may be completed in a single cycle, the processor may issue and retire instructions on each cycle, thereby achieving effective single-cycle execution.

Some RISC processors have overlapped instruction execution, in which load operations may allow the execution of subsequent, unrelated instructions to continue before the data requested by the load has been returned from memory.

This allows these instructions to overlap the load, thereby improving processor performance. Due to their low power consumption and computing power, RISC processors are becoming widely used, particularly in embedded computer systems, and many RISC attributes are appearing in what are traditionally CISC architectures such as with the Intel Pentium.

If power consumption needs to be low, then RISC is probably the better architecture to use. These processors have instruction sets and architectures optimized for numerical processing of array data. They often extend the Harvard architecture concept further by not only having separate data and code spaces, but also by splitting the data spaces into two or more banks. This allows concurrent instruction fetch and data accesses for multiple operands. DSPs have special hardware well suited to numerical processing of arrays.

They often have hardware looping , whereby special registers allow for and control the repeated execution of an instruction sequence.

This is also often known as zero-overhead looping , since no conditions need to be explicitly tested by the software as part of the looping process. DSPs often have dedicated hardware for increasing the speed of arithmetic operations. DSP processors are commonly used in embedded applications, and many conventional embedded microcontrollers include some DSP functionality. Memory Memory is used to hold data and software for the processor. There is a variety of memory types, and often a mix is used within a single system.

Some memory will retain its contents while there is no power, yet will be slow to access. Other memory devices will be high-capacity, yet will require additional support circuitry and will be slower to access.

Still other memory devices will trade capacity for speed, yielding relatively small devices, yet will be capable of keeping up with the fastest of processors. Memory chips can be organized in two ways, either in word-organized or bit-organized schemes. In the word-organized scheme, complete nybbles, bytes, or words are stored within a single component, whereas with bit-organized memory, each bit of a byte or word is allocated to a separate component Figure In both cases, each chip has exactly the same storage capacity, but organized in different ways.

However, because the DRAMs are organized in parallel, they are accessed simultaneously. It is common practice for multiple DRAMs to be placed on a memory module. This is the common way that DRAMs are installed in standard computers.

The common widths for memory chips are x1, x4, and x8, although x16 devices are available. A bit-wide bus can be implemented with thirty-two x1 devices, eight x4 devices, or four x8 devices.

It is where the processor may easily write data for temporary storage. RAM is generally volatile, losing its contents when the system loses power. Any information stored in RAM that must be retained must be written to some form of permanent storage before the system powers down.

There are special nonvolatile RAMs that integrate a battery-backup system, such that the RAM remains powered even when the rest of the computer system has shut down. SRAMs use pairs of logic gates to hold each bit of data.

S.Chand's Computer Architecture and Maintenance 12113-Msbte, 1/e

SRAMs are the fastest form of RAM available, require little external support circuitry, and have relatively low power consumption. Their drawbacks are that their capacity is considerably less than DRAM, while being much more expensive.

Their relatively low capacity requires more chips to be used to implement the same amount of memory. A modern PC built using nothing but SRAM would be a considerably bigger machine and would cost a small fortune to produce.

It would be very fast, however. DRAM uses arrays of what are essentially capacitors to hold individual bits of data.

The capacitor arrays will hold their charge only for a short period before it begins to diminish. Therefore, DRAMs need continuous refreshing, every few milliseconds or so.

Post graduation. MCA Science. First Standard. Second Standard. Third Standard. Fourth Standard. Fifth Standard. Sixth Standard. Seventh Standard. Eighth Standard. Ninth Standard. Tenth Standard. Management Studies. Pre School. Picture books. Board books. Story books. Handwriting books. Activity books. Nursery Rhymes. Colouring books. Identify books. School TextBooks. Subject Based. IBPS Clerk. SBI PO.

SBI SO. SBI Clerk. RBI Assistant. Defence Services. Indian Air Force. Police Services Examinations. Indian Navy. Intelligence Agencies. Border Security Force and related. Indian Army. Indian Coast Guards. Engineering Entrance. JEE Main and Advanced. Medical Entrance. B Pharma. Management Entrance. Law Entrance. Judicial Services.The subsystems that you will typically find in microcontrollers will be discussed in the coming chapters. Some memory will retain its contents while there is no power, yet will be slow to access.

Colouring books. Shining ultraviolet light through a small window on the top of the chip can erase the EPROM, allowing it to be reprogrammed and reused. Author s : Philipp Hafliger, Dag Langmyhr and Omid Mirmotahari Pages Computer System Architecture Lecture Notes This note contains the study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems.

Due to their low power consumption and computing power, RISC processors are becoming widely used, particularly in embedded computer systems, and many RISC attributes are appearing in what are traditionally CISC architectures such as with the Intel Pentium.

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